TITLE: Project #4: Two Digit HEX Counter
AUTHOR: Chuck McManis
LAST UPDATE: 10-Apr-2001


This project builds a two digit hex counter that can count up and down. Further, the count can reset at any time and held on the rising edge of any clock. I synthesized it with the Synopsys compiler after the XST fiasco in project 3, however ran into another interesting bit.

The XST compiler allows you to map a port pin to a constant, as in:

ux: hex_display port map (blank => '0', test => '0', ...);

This is quite handy if you aren’t going to be using those pins, further the place and route code usually can optimize out the logic that would have been driven by these pins.

But the fancy (and expensive) Synopsys compiler won’t accept that, nope. Instead you have to write:

    signal bogus_signal : std_logic;
    bogus_signal <= '0'; -- always zero this one
    ux: hex_display port map (blank=> bogus_signal, test => bogus_signal,...);

Where is the advantage in that? Ashenden indicates that strict VHDL syntax would not allow what the XST guys allow, but heck it is effectively the same thing? Why not support this small bit of syntactic sugar? The bottom line here is:

VHDL compilers are all different, in spite of the hype it is just as impossible to write portable VHDL code as it is C code.


Design an 8 bit counter that displays its current count on two LED displays. The counter should count at a rate of 10 counts/second. Use the CLOCK_10HZ and HEX_DISPLAY entities in this project. The pin-out for this chip is as follows:

Signal Assignments
Pin Direction Description
SRC_CLK IN This is a 24Mhz input clock.
OUT Two seven segment displays. Display zero is the high order display and display one is the low order display.
CLR IN When asserted "low" this pin should reset the count to "00."
RUN IN When this pin is asserted "high" the counter runs, when it is "low" the counter should hold its count.
DIR IN When this pin is asserted "high" the counter should count "up" (from 0 up), when it is "low" the counter should count down from "FF" to 0.

This project creates another bit of eye-candy for you to look at, a couple of digits counting up, or down, in hexadecimal.


The neat thing about this project is that it gets a bit more complicated in what it combines. It leads naturally into the next project (a multi-digit display) and has a twist that you need are including both a reset circuit (CLR) and a gating circuit (RUN).


The hex counter provides an 8 bit count for the incoming clock. With a minor modification it can be adapted to be a pulse accumulator, counting the number of pulses that happen in unit time.

In this circuit the SRC_CLK pin is again the 24Mhz master clock from the SPARTAN2+ board. If you’re using the XESS board then it would be the 12Mhz clock on that board, The RUN pin should enable/disable the counting logic and the DIR pin controls whether the counter goes up or down.

Going Further

The basic up/down counter is a staple in a lot of circuits you may build. In robots they are used by encoders to determine wheel position. Some other ideas::