Description

This represents a different, and better, way of synthesizing a HEX decoder.

Schematic Representation of the HEX Display

The Source Code

-- HEX Decoder for 7 segment displays       Chuck McManis 8-Mar-2001
--
-- This is an alternate implemntation of the HEX decoder. It uses concurrent
-- signal assignment rather than the process structrure that the primary
-- implementation uses. On the free tools it uses one less block than the
-- other implementation, but on the synopsis tools its the same as the
-- 'best' implemention.
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity hex2_display is
    Port (  test : in std_logic;
            blank : in std_logic;
            data : in std_logic_vector(3 downto 0));
            segs : out std_logic_vector(6 downto 0);
end hex2_display;

architecture behavioral of hex2_display is

begin
    segs <= "0000000" when blank = '1' else
            "1111111" when test = '1' else
            "1111110" when data = "0000" else
            "0110000" when data = "0001" else
            "1101101" when data = "0010" else
            "1111001" when data = "0011" else
            "0110011" when data = "0100" else
            "1011011" when data = "0101" else
            "1011111" when data = "0110" else
            "1110000" when data = "0111" else
            "1111111" when data = "1000" else
            "1110011" when data = "1001" else
            "1110111" when data = "1010" else
            "0011111" when data = "1011" else
            "1001110" when data = "1100" else
            "0111101" when data = "1101" else
            "1001111" when data = "1110" else
            "1000111";
end behavioral;

License

This work is licensed under a Creative Commons Attribution-NonCommercial 3.0 Unported License. You are free to play around with it and modify it but you are not licensed to use it for commercial purposes. Click the link above for more details on your rights under this license.