TITLE: The PIC Instruction Set Architecture
AUTHOR: Chuck McManis
LAST UPDATE: 10-Jun-2013


The PIC instruction set architecture (ISA) has a couple of ‘flavors’ with 12, 14, and 16 bit versions. Generally they more bits give the chip more memory addressing but it they include some additional instructions.

Given that a running system based on the PIC was fairly easy to implement, and in the PIC18F54 had an EEPROM memory rather than a EPROM or OTPROM memory, so it could be reprogrammed without a UV lamp to erase it, it became a cost effective way to get into simple controller design. When personal computers had parallel ports, David Tait designed a very simple to use ‘bit banged’ programmer that ran with some clever software and that could program the ’84. The free tools from Microchip completed the story and many hundreds, if not thousands, of small robots and sensors will built with PIC chips.

Idiosyncracies of the Architecture

The PIC chips were acquired by Microchip from General Instrument. Designed to be a low gate count (and thus cheap) peripheral integrated circuit (aka PIC), these chips were not built to be programmed with a high level language. Instead the designer/programmer was expected to master the machine language that General Instrument had devised. Microchip’s initial contribution to the chips was to make them programmable via EPROM rather than by ROM masks. The original architecture as desribed by General Instrument in the 1982 Microelectronics Catalog for the PIC1650A:

All in a 40 pin Dual-inline package. So pretty giant by todays standards.

The defining feature, that General Instrument considered a feature, was that all of RAM was considered one giant register bank. Every instruction which operated on a register (which meant all of RAM) could leave the results of that operation either in the register, or in a special register in the arithmetic logic unit named ‘W’. W as not not explictly accessible but it was implictly accessible. Thus it wasn’t really a register so much as it was “the other place” an operand could be. This concept has been used, and abused to make various things possible. Testing a register for zero became a dance of OR’ing that register with 0 but storing the result in W (leaving the register untouched but the flags set). For a more colorful story about how convoluted that gets, read the article on 16 bit arithmetic!

The other place this feature really crimped Microchip’s abitlity to innvoate was that having the offsets for registers hard coded into 7 bits of the instruction meant that you could only ever access 128 different registers. To overcome that limitation Microchip added the notion of a ‘bank’ (up to four of them in some chips) which could be set prior to accessing memory.

For software, this created a challenge when dealing with interrupts because you needed to know exactly where your data was, so every interrupt routine often started by setting the processor to a ‘known’ bank and then restoring the previous bank when exiting.

Basic Instructions

With only 35 unique instructions the PIC instruction set is pretty compact. That however does not make it particularly simple. Nearly every instruction has the opportunity to operated either on W or one of the 128 currently addressable RAM locations (called Register Files or File Registers by Microchip). Perhaps the most general description will be in the PIC16F628A data sheet, but the basic instructions (sans clock counts or which flags they affect) are reproduced below.

PIC 14-bit Instruction Summary
Byte Oriented Register File Operations
Op CodeDescription
ADDWF f, d Add W to f
ANDWF f, dAND W with f
CLRF f Clear f
CLRW Clear W
COMF f, dComplement f
DECF f, dDecrement f
DECFSZ f, dDecrement f, Skip if 0
INCF f, dIncrement f
INCFSZ f, dIncrement f, Skip if 0
IORWF f, dInclusive OR W with f
MOVF f, dMove f
MOVWF f Move W to f
NOP No Operations
RLF f, dRotate Left f through Carry
RRF f, dRotate Right f through Carry
SUBWF f, dSubtract W from f
SWAPF f, dSwap nybbles in f
XORWF f, dExclusive Or f
Bit Oriented Register File Operations
Op CodeDescription
BCF f, b Bit Clear f
BSF f, b Bit Set f
BTFSC f, b Bit test F, Skip if clear
BTFSS f, b Bit test F, skip if set
Operations with Constants & Control
Op CodeDescription
ADDLW cAdd constant c to W
ANDLW cAND constant c to W
IORLW cOR constant c with W
MOVLW cMove constant c into W
SUBLW cSubtract constant c from W
XORLW cExclusive or constant c with W
Flow of Control Operations
Op CodeDescription
CALL addrCall address addr
CLRWDT Clear Watchdog Timer
GOTO addrGoto address addr
RETFIEReturn from Interrupt (re-enable Interrupts)
RETLW cReturn with constant c in W
RETURNReturn from subroutine
SLEEPPut processor to Sleep